A formal method for designing sequential circuits from synchronous flip-flops such as the J-K type using a hybrid synchronous-asynchronous technique

A formal method is presented which simplifies the realization of many counter sequences in asynchronous form from synchronous flip-flops such as the J-K or D type, without requiring the use of preset or clear connexions to establish the sequence. The method is demonstrated by using the procedure to obtain asynchronous circuits in terms of J-K flip-flops for counters operating in the 8-4-2-1 and 5-4-2-1 b.c.d. codes. Though circuits for these sequences are well known the design procedure is of educational interest and offers alternative circuits for the sequences. The procedure is equally applicable to the realization of many other sequences.