DocumentCode
1477631
Title
Universal Test Interface for embedded-DRAM testing
Author
Miyano, Shinji ; Sato, Katsuhiko ; Numata, Kenji
Author_Institution
Toshiba Corp., Yokohama, Japan
Volume
16
Issue
1
fYear
1999
Firstpage
53
Lastpage
58
Abstract
Because the configurations of embedded DRAM macros vary for each product, designers normally must customize the test circuitry for each product. The authors have developed circuitry (Universal Test Interface) that unifies testing regardless of the DRAM configuration and the number of macros on a chip. The Universal Test Interface alleviates the contradiction inherent in embedded DRAM testing
Keywords
DRAM chips; application specific integrated circuits; embedded systems; integrated circuit testing; macros; DRAM configuration; Universal Test Interface; embedded DRAM macros; embedded DRAM testing; test circuitry; Application specific integrated circuits; Assembly; Bandwidth; Circuit testing; Fuses; Logic testing; Pins; Product design; Random access memory; Tellurium;
fLanguage
English
Journal_Title
Design & Test of Computers, IEEE
Publisher
ieee
ISSN
0740-7475
Type
jour
DOI
10.1109/54.748805
Filename
748805
Link To Document