SRAM cell for high noise margin and soft errors tolerance in nanoscale technology

In this paper, we present various techniques used to improve SRAM stability and their trade-offs to conventional 6T-SRAM. The performance of these structures is analyzed in terms of reliability, speed, size, and leakage power by using HSPICE simulator in 90 nm and 32 nm CMOS processes. In 90 nm technology, 8T cell shows an improvement of 2.1X in read margin and an area penalty of over 24% compared to 6T cell. For 32 nm process, the improvement is 9.78X and the area overhead is 29%. On the other hand, 8T cell also allows different words to be read and written simultaneously while taking advantages of LS-layout topology of 6T cell. Therefore, 8T cell is the most suited to replace 6T structure in the next advanced CMOS processes. In addition, the study also shows that a 12T SRAM structure with high read stability and less sensitive to soft errors is totally feasible.