Title :
Fine-Grained Activation for Power Reduction in DRAM
Author :
Cooper-Balis, Elliott ; Jacob, Bruce
Author_Institution :
Univ. of Maryland, College Park, MD, USA
Abstract :
This DRAM architecture optimization, which appears transparent to the memory controller, significantly reduces power consumption. With trivial additional logic, using the posted-CAS command enables a finer-grained selection when activating a portion of the DRAM array. Experiments show that, in a high-use memory system, this approach can reduce total DRAM device power consumption by up to 40 percent.
Keywords :
DRAM chips; energy conservation; memory architecture; optimisation; DRAM architecture optimization; DRAM array; DRAM power reduction; fine grained activation; high use memory system; memory controller; posted CAS command; power consumption reduction; trivial additional logic; DRAM; DRAMsim; fine-grained activation; low-power design; memory system; posted-CAS command;
Journal_Title :
Micro, IEEE
