A proposed RISC instruction set architecture for the MAC unit of 32-bit VLIW DSP processor core

Multiplier-accumulator is a specific hardware unit that performs a common operation - computing the product of two numbers and adding that product to an accumulator. Especially, in digital signal processing applications which consist of a large number of convolution operations, the emergence of MAC unit contributes greatly to the high performance of the systems. This work is about an implementation for a specific MAC unit based on the proposed RISC instruction set architecture (ISA) of 32-bit VLIW Fixed-point DSP processor core presented in our previous work. The computational unit is designed to be flexible for 32-bit/16-bit/8-bit data computations. The implementation is verified to function correctly not only in Modelsim software but also on Altera Cyclone II (2C35) FPGA board.