Effects of Device Structure and Back Biasing on HCI and NBTI in Silicon-on-Thin-BOX (SOTB) CMOSFET

Author

Ishigaki, Takashi ; Tsuchiya, Ryuta ; Morita, Yusuke ; Sugii, Nobuyuki ; Kimura, Shin Ichiro

Author_Institution

Central Res. Lab., Hitachi Ltd., Kokubunji, Japan

Volume

58

Issue

4

fYear

2011

fDate

4/1/2011 12:00:00 AM

Firstpage

1197

Lastpage

1204

Abstract

The silicon-on-thin-buried-oxide (SOTB) CMOSFET is one of the strong candidates for further scaling because of its smallest Vth variation and back-bias controllability. This study focuses on its reliability, i.e., the hot-carrier-injection (HCI) degradation for the n-channel MOS and the negative-bias temperature instability (NBTI) for p-channel MOS. A comparison of the SOTB CMOSFET with a conventional bulk CMOSFET showed that the SOTB structure, which has a low-dose channel without a halo implant, produces higher reliability. The impact of the wide-range back biasing in SOTB devices on reliability was determined, i.e., the back biasing changes the mechanism of the HCI degradation but does not affect the NBTI degradation.

Keywords

MOSFET; hot carriers; semiconductor device reliability; CMOSFET; HCI degradation; NBTI; SOTB device; Si; halo implant; hot-carrier-injection; n-channel MOS; negative-bias temperature instability; p-channel MOS; reliability; silicon-on-thin-BOX; wide-range back biasing controllability; CMOSFETs; Degradation; Human computer interaction; Implants; Logic gates; MOSFET circuits; Back bias; back gate; fully depleted silicon on insulator (FD-SOI); hot-carrier injection (HCI); negative-bias temperature instability (NBTI); reliability; thin buried oxide (BOX);

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2011.2107520

Filename

5737864