DocumentCode
1478810
Title
1:4 demultiplexer architecture for Gbit/s lightwave systems
Author
Runge, K.
Author_Institution
Bellcore, Red Bank, NJ, USA
Volume
27
Issue
9
fYear
1991
fDate
4/25/1991 12:00:00 AM
Firstpage
753
Lastpage
755
Abstract
A high speed 1:4 demultiplexer IC architecture featuring output bit alignment, reduced gate count, and improved timing over a conventional tree-type architecture demultiplexer is presented. Simulation results at 20 Gbit/s are obtained using an HBT process. The architecture can be directly extended to higher order demultiplexers, and is applicable to other processes supporting current-mode logic.
Keywords
bipolar integrated circuits; integrated logic circuits; multiplexing equipment; optical communication equipment; 1:4 demultiplexer; 20 Gbit/s; HBT process; IC architecture; current-mode logic; demultiplexer architecture; improved timing; lightwave systems; output bit alignment; reduced gate count; simulation results;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19910468
Filename
74901
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