Abstract :
A design for a 128-bit m.o.s. associative memory is described. The memory array can be integrated on a 1.6 × 2.9 mm (63 × 114 mil) chip using standard silicon-gate m.o.s. fabrication technology. The basic memory cell is dynamic in operation, but external refresh circuitry is not required. Computer simulation studies predict match and read access times of 10 ns, and a write `toggle¿ time of 25 ns. A design for a cheap interface buffer circuit is also described. With these two designs it is possible to build a low-cost associative memory array, organized as 256 words of 256 bits each, which is TTL compatible and will operate with a 100 ns cycle time.
