Advanced SoC virtual prototyping for system-level power planning and validation

Today´s electronic devices imply significant efforts in pre-silicon low-power design. Key techniques such as scaling of operating points, or switching power off to unused blocks play a major role and are usually managed at entire system scope. Finally, the delay paid in today´s design cycles is the time needed for verification, since power-aware design starts late and, hence, relies on painful system-level simulation performances. In this work, we describe a SystemC-based virtual prototyping approach capturing low-power design characteristics in earlier design stages. In contrast to existing solutions, we focus on advanced modeling techniques such as blocking transactions and temporal decoupling, which are integral part of modern industrial-sized designs. As proof of concept, we use representative virtual platform models at several levels of abstraction. Based on empirical results we argue that our annotations cause reasonable overhead, but provides sufficient details to validate typical power planning scenarios.