A lightweight-system-level power and area estimation methodology for application specific instruction set processors

Detailed power estimation is a tedious and time consuming task in modern ASIP design. To facilitate this process, we present faster and fully automated estimation models for use at system level. In the first step of our approach, we calculate normalized values for all the basic design components of the processor that are related to power and area (e.g. memories, register files, function units, etc). These normalized values are estimated based on processors with different configurations (e.g., different memory sizes) and then stored in a database. Later, in the second step, this information is used to estimate the power of new derived architectures. To that end, we combine the previously calculated normalized power data with the component configurations and switching information from system-level simulation. The approach is demonstrated on the example of an Intel ASIP design flow (Silicon Hive). We report power and area estimates for four different ASIP designs. The mean error of the area prediction is 10%, while the mean error in power prediction is 15%.