Low-power design methodology for CML and ECL circuits

This paper presents a design methodology to enable the design of power efficient, high-speed CML/ECL circuits. It covers library requirements as well as proposed architectural improvements for power optimization. At transistor level, a voltage supply reduction from 3.3V to 2.5V is enabled by modifying classical three-level stack CML latch topology. Secondly, implementing several speed classes using different load resistor variants of most important gates allows for more efficient balancing of critical paths. The methodology is exemplary demonstrated on an 4:1 Serializer with 2 times 2×4 bit FIFO designed in low-cost 0.25 μm SiGe BiCMOS process. AMS schematic simulation results show that both approaches lead to a reduction of the overall current of 39% to 58.68 mA, resulting in a total power dissipation of 146.70mW. The maximal data rate of 12.5 Gb/s is achieved, whereas 54% of the total power could be saved compared to baseline 3.3V design.