Power-efficient turbo-decoder design based on algorithm-specific power domain partitioning

Frequency-voltage scaling is an efficient technique to tackle the large power consumption of turbo decoders implemented in digital integrated circuits for wireless communications. In this paper, we propose a novel design approach that improves the efficacy of frequency-voltage scaling in turbo decoders. In particular, we present a turbo decoder based on an improved soft-output Viterbi algorithm (SOVA) and describe a VLSI implementation where we integrate the SOVA-specific large amount of short signal paths in a separate power domain. As opposed to the standard approach, where the voltage of the turbo decoder is scaled on a per-block basis, this optimization enables one to scale the voltage of the short signal paths more aggressively than the voltage of the timing-critical circuits. Silicon measurements of a fabricated proof-of-concept 180nm CMOS ASIC prototype optimized for 3GPP demonstrate that the presented SOVA-specific power domain partitioning enables additional power savings of 25% compared to the conventional block-level voltage scaling. These power savings can be extracted even at maximum operating frequency.