DocumentCode
1480656
Title
Power Variability in Contemporary DRAMs
Author
Gottscho, Mark ; Kagalwalla, Abde Ali ; Gupta, Puneet
Author_Institution
Dept. of Electr. Eng., Univ. of California, Los Angeles, CA, USA
Volume
4
Issue
2
fYear
2012
fDate
6/1/2012 12:00:00 AM
Firstpage
37
Lastpage
40
Abstract
Technology scaling has led to significant variability in chip performance and power consumption. In this work, we measured and analyzed the power variability in dynamic random access memories (DRAMs). We tested 22 double date rate third generation (DDR3) dual inline memory modules (DIMMs), and found that power usage in DRAMs depends on both operation type (write, read, and idle) as well as data, with write operations consuming more than reads, and 1s in the data generally costing more power than 0s. Temperature had little effect (1-3%) across the C to 50 C range. Variations were up to 12.29% and 16.40% for idle power within a single model and for different models from the same vendor, respectively. In the scope of all tested 1 gigabyte (GB) modules, deviations were up to 21.84% in write power. Our ongoing work addresses memory management methods to leverage such power variations.
Keywords
DRAM chips; power aware computing; storage management; DDR3; DIMM; chip performance; contemporary DRAM; double date rate third generation dual inline memory modules; dynamic random access memories; memory management methods; operation type; power consumption; power variability; technology scaling; write operations; Hardware; Memory management; Power demand; Random access memory; Software; Temperature distribution; Very large scale integration; Double data rate third generation (DDR3); dynamic random access memory (DRAM); power; variability;
fLanguage
English
Journal_Title
Embedded Systems Letters, IEEE
Publisher
ieee
ISSN
1943-0663
Type
jour
DOI
10.1109/LES.2012.2192414
Filename
6176200
Link To Document