Title :
Regular VLSI architectures for multiplication modulo (2n+1)
Author :
Curiger, Andreas V. ; Bonnenberg, Heinz ; Kaeslin, Hubert
Author_Institution :
Swiss Federal Inst. of Technol., Zurich, Switzerland
fDate :
7/1/1991 12:00:00 AM
Abstract :
The authors describe VLSI architectures for multiplication modulo p, where p is a Fermat prime. With increasing p , ROM-based table lookup methods become unattractive for integration due to excessive memory requirements. Three novel methods are discussed and compared to ROM implementations with regard to their speed and complexity characteristics. The first method is based on an ( n+1)×(n+1)-bit array multiplier, the second on modulo p carry-save addition, and the third on modulo (p -1) carry-save addition using a bit-pair recoding scheme. All allow very high throughputs in pipelined implementations. While the former is very convenient for CAD (computer-aided design) environments providing a pipelined multiplier macrocell, the latter two are well-suited to full-custom implementation
Keywords :
VLSI; digital arithmetic; integrated logic circuits; multiplying circuits; parallel architectures; pipeline processing; CAD; Fermat prime; VLSI architectures; array multiplier; bit-pair recoding scheme; carry-save addition; complexity characteristics; computer-aided design; full-custom implementation; multiplication modulo; pipelined implementations; pipelined multiplier macrocell; speed; Arithmetic; Cryptography; Error correction codes; Flow graphs; Hardware; Macrocell networks; Read only memory; Space technology; Throughput; Very large scale integration;
Journal_Title :
Solid-State Circuits, IEEE Journal of
