A general-purpose high-speed equalizer

Author

Maginot, Serge ; Balestro, Freddy ; Joanblanq, Christophe ; Senn, Patrice ; Palicot, Jacques

Author_Institution

CNET, Meylan, France

Volume

26

Issue

3

fYear

1991

fDate

3/1/1991 12:00:00 AM

Firstpage

209

Lastpage

216

Abstract

The circuit presented is a high-speed self-adaptive filter achieving equalization over a wide range of signals, with a frequency of up to 40.5 MHz, as for the European D2-MAC and high-definition multiplexed analog components (HD-MAC) transmission standards. The circuit is a self-adaptive 16-tap transversal filter achieving equalization on any 8-b coded signal. It contains periodically a window of binary or duobinary data samples, such as the D, D2, and HD-MAC signals. This chip includes a delay line of 240 8-b data samples which are used for the internal gradient computations. Only linear distortions (echos) can be corrected by this chip. This 105000-transistor chip has been designed in a CMOS 1.0-μm technology and is being used in a D2-MAC reception environment

Keywords

CMOS integrated circuits; adaptive filters; equalisers; 1.0 micron; CMOS; D2-MAC; delay line; duobinary data samples; equalization; equalizer; high-definition multiplexed analog components; internal gradient computations; linear distortions; reception environment; self-adaptive filter; transversal filter; Adaptive equalizers; Adaptive filters; Bandwidth; CMOS technology; Circuits; Frequency; Machine vision; Sampling methods; Standards development; Transversal filters;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.74998

Filename

74998