Title :
Reliability Investigation of Large GaAs Pixel Detectors Flip-Chip-Bonded on Si Readout Chips
Author :
Klein, Matthias ; Hutter, Matthias ; Engelmann, Gunter ; Fritzsch, Thomas ; Oppermann, Hermann ; Dietrich, Lothar ; Wolf, M. Jürgen ; Brämer, Birgit ; Dudek, Rainer ; Reichl, Herbert
Author_Institution :
Fraunhofer Inst. fur Zuverlassigkeit und Mikrointegration, Berlin, Germany
fDate :
3/1/2011 12:00:00 AM
Abstract :
Lead-free reflow soldering techniques applying AuSn as well as SnAg electroplated bumps were chosen for the evaluation of the flip-chip-bonding process for X-ray pixel detectors. Both solders can be used in pick-and-place processes with a subsequent batch reflow suitable for high-volume production. AuSn solder was selected because of its fluxless bondability, good wettability, and self-alignment process capability, and SnAg solder was chosen for its more ductile behavior and lower yield stress compared to AuSn. GaAs test chips with daisy chain and four-point Kelvin probe structures together with appropriate Si test substrates were designed, manufactured, and bumped. Test chips with 55 and 170 μm pitch and different chip sizes (maximum 16.3 down to 4 mm square) were used. AuSn bumps were deposited by electroplating (first Au and a thin Sn layer on top). Thick Au bonding pads were formed on substrate side in case of AuSn bumps. Two under-bump metallizations (UBMs) were used for the SnAg samples: Cu and Ni. Finite element (FE) simulation was performed comparing AuSn and SnAg interconnections and different chip sizes. A local model was designed for bump interconnection and a global octant model for the assembly process. Very high values were calculated for the peel stress using AuSn bumps. SnAg bumps, on the other hand, showed 3-5 times reduction in peel stress depending on the chip size. A flip-chip-bonding process setup was carried out for both solder types (AuSn as well as SnAg), with an analysis of the samples by electrical measurements, cross-sectioning, and scanning electron microscopy. Due to the different coefficients of the thermal expansion of GaAs and Si, no stable bonding process was obtained for the AuSn modules as already predicted by the FE simulation. With increasing chip size, failures like pad lift or cracking of the GaAs bulk material were observed. In comparison, the SnAg samples showed good bonding results. This technology was then selected- to assemble test modules for thermal cycling between -55 and +125°C comparing Cu and Ni as UBM. The modules were qualified by electrical monitoring as well as cross sectioning. More than 200 cycles were reached by the 55-μm pitch 16.3-mm square bonded GaAs chips and about 400 by the smallest 4-mm square chips, although no underfilling was used. The dominant failure mode was fracture within the solder. Based on experimental and simulation results, functional 256 × 256 GaAs pixel detectors with a chip size of 14 mm × 14 mm were assembled on Si readout chips using SnAg bumps on a Cu UBM. Finally, these X-ray image sensors were wire-bonded to a printed circuit board and successfully tested, showing an yield (at the pixel level) of about 98%.
Keywords :
III-V semiconductors; assembling; ductility; electroplating; elemental semiconductors; finite element analysis; flip-chip devices; gallium arsenide; gold compounds; image sensors; integrated circuit bonding; integrated circuit interconnections; integrated circuit reliability; integrated circuit testing; lead bonding; printed circuits; reflow soldering; scanning electron microscopy; silicon; tin compounds; yield stress; AuSn; FE simulation; GaAs; Si; SnAg; X-ray image sensors; X-ray pixel detectors; assembly process; batch reflow; bonding pads; bulk material cracking; bump interconnection; daisy chain structures; ductile behavior; electrical measurements; electrical monitoring; electroplated bumps; electroplating; finite element simulation; flip-chip bonding process; four-point Kelvin probe structures; fracture; global octant model; high-volume production; lead-free reflow soldering techniques; pad lift; peel stress; pick-and-place processes; printed circuit board; reliability investigation; scanning electron microscopy; self-alignment process capability; silicon readout chips; silicon test substrates; size 170 mum; size 55 mum; test chips; thermal expansion; underbump metallizations; wire bonding; yield stress; Copper; Gallium arsenide; Gold; Nickel; Pixel; Silicon; Stress; AuSn; SnAg; flip-chip; pixel detector; reliability;
Journal_Title :
Components, Packaging and Manufacturing Technology, IEEE Transactions on
DOI :
10.1109/TCPMT.2011.2108299