Implementation of a learning Kohonen neuron based on a new multilevel storage technique

A compact implementation of a fully parallel Kohonen network with learning capabilities is described. Implementation issues concerning general neural networks are briefly explored, and an original mixed analog and digital technique for storing discrete voltages on a capacitor is presented. The limitations are discussed, and measurements on the storage dynamics are reported, showing that 8 b of resolution can be achieved. This technique is applied to the realization of a neuron dedicated to Kohonen maps. This neuron has been implemented in a standard 2-μm CMOS technology, and the synaptic functions are very dense. The implementation uses a standard 8-b integer arithmetic. Efficient and consistent encoding of the information, dynamic storage, and the adaptation of the synaptic weights and the synaptic multipliers use simple circuitry, thus leading to a low number of transistors