Title :
A comprehensive CAD system for high-performance 300 K-circuit ASIC logic chips
Author :
Panner, Jeannie H. ; Abato, Richard P. ; Bassett, Robert W. ; Carrig, Keith M. ; Gillis, Pamela S. ; Hathaway, David J. ; Sehr, Terrence W.
Author_Institution :
IBM Gen. Technol. Div., Essex Junction, VT, USA
fDate :
3/1/1991 12:00:00 AM
Abstract :
A computer-aided design (CAD) system has been developed to support design of CMOS application-specific integrated circuit (ASIC) logic chips containing more than 300 K equivalent two-input NANDs with 180-ps typical gate delays. The underlying technology is a 0.8-μm, four-level-metal, single-poly CMOS process, with a 0.45-μm nominal effective channel length and 180-ps typical gate delay. Both standard-cell and gate-array circuit libraries are provided, including fixed and growable memory macros. Key new system features are described in the areas of high-level design and synthesis, delay calculation and timing analysis, timing guidance to physical design, physical design, clock construction, and test generation. Early processing results are reported for several test chips, including a 9.7-mm 2-million-transistor chip and a 14.5-mm 300 K-equivalent-gate chip
Keywords :
CMOS integrated circuits; NAND circuits; application specific integrated circuits; circuit CAD; logic CAD; logic arrays; 0.8 micron; 180 ps; 300 K-circuit ASIC logic chips; CAD system; clock construction; delay calculation; gate delay; gate delays; gate-array circuit libraries; nominal effective channel length; single-poly CMOS process; standard-cell; test generation; timing analysis; timing guidance; two-input NANDs; Application specific integrated circuits; CMOS logic circuits; CMOS process; CMOS technology; Circuit testing; Delay; Design automation; Integrated circuit technology; Logic design; Timing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
