Logic synthesis of race-free asynchronous CMOS circuits

Author

Piguet, Christian

Author_Institution

Centre Suisse d´´Electron. et de Microtech., Neuchatel, Switzerland

Volume

26

Issue

3

fYear

1991

fDate

3/1/1991 12:00:00 AM

Firstpage

371

Lastpage

380

Abstract

A synthesis method for generating race-free asynchronous CMOS circuits that are independent of the internal and output delays is presented. The design method is based on the properties of the negative gates. An inertial delay is associated with each negative gate in a CMOS circuit. Such a gate model is quite realistic. The basic principle of the method presented is to augment and to modify the original flow table in such a way that the obtained logic diagram contains only negative gates. In addition, the synthesis method is capable of avoiding any race, and consequently any critical race or hazard. The method minimizes the number of internal variables and therefore the number of gates, providing new simple cells for fast and low-power integrated circuits

Keywords

CMOS integrated circuits; hazards and race conditions; integrated logic circuits; logic design; logic gates; critical race; flow table; gate model; inertial delay; internal variables; logic diagram; low-power integrated circuits; negative gate; output delays; race-free asynchronous CMOS circuits; synthesis method; Asynchronous circuits; CMOS logic circuits; CMOS technology; Circuit synthesis; Delay; Hazards; Integrated circuit synthesis; Parasitic capacitance; Sequential circuits; Switches;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.75016

Filename

75016