A 12 MHz data cycle 4 Mb DRAM with pipeline operation

A 12 MHz data-cycle 4 Mb DRAM (dynamic RAM) with pipeline operation was designed and fabricated using 0.8 μm twin-tub CMOS technology. The pipeline DRAM outputs data corresponding to addresses that were accepted in the previous inverted random access storage (RAS) input cycle. The latter half of the previous read operation and the first half of the next read operation take place simultaneously, so the inverted RAS input cycle time is reduced. This pipeline DRAM technology needs no additional chip area and no process modification. A 95 ns inverted RAS input cycle time was obtained under worst conditions while this value is 125 ns for conventional DRAMs