An 8 ns 4 Mb serial access memory

Author

Kuriyama, Hirotada ; Hirose, Toshihiko ; Murakami, Shuji ; Wada, Tomohisa ; Fujita, Koreaki ; Nishimura, Yasumasa ; Anami, Kenji

Author_Institution

Mitsubishi Electr. Corp., Hyogo, Japan

Volume

26

Issue

4

fYear

1991

fDate

4/1/1991 12:00:00 AM

Firstpage

502

Lastpage

506

Abstract

A new architecture for serial access memory is described that enables a static random access memory (SRAM) to operate in a serial access mode. The design target is to access all memory address serially from any starting address with an access time of less than 10 ns. This can be done by all initializing procedure and three new circuit techniques. The initializing procedure is introduced to start the serial operation at an arbitrary memory address. Three circuit techniques eliminate extra delay time caused by an internal addressing of column lines, sense amplifiers, word lines, and memory cell blocks. This architecture was successfully implemented in a 4-Mb CMOS SRAM using a 0.6 μm CMOS process technology. The measured serial access time was 8 ns at a single power supply voltage of 3.3 V

Keywords

CMOS integrated circuits; SRAM chips; VLSI; 0.6 micron; 3.3 V; 4 Mbit; 8 ns; CMOS; SRAM; initializing procedure; serial access memory; serial access mode; serial memory address; single power supply voltage; static RAM; static random access memory; CMOS process; CMOS technology; Circuits; Delay effects; Memory architecture; Power measurement; Power supplies; Random access memory; SRAM chips; Time measurement;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.75046

Filename

75046