A 2-ns 16K bipolar ECL RAM with reduced word-line voltage swing

A reduced word-line voltage swing (RWS) circuit configuration that results in a high-speed bipolar ECL (emitter coupled logic) RAM is proposed. The write operation can be performed with the configuration in the condition of reduced word-line voltage swing, which causes write operation error in conventional circuit configurations. The proposed configuration cuts off the hold current of the selected memory cell, and then the low-voltage node is charged up through the load p-n-p transistor. A 16-kb ECL RAM with a p-n-p loaded memory cell was fabricated by advanced silicide-base transistor (ASBT) process technology. A 2-ns access time was obtained with 1.8-W power consumption in which the word-line voltage swing was reduced by 0.7 V from a conventional case. Simulation results show that the access time is improved by 25% compared with a conventional case. Simulation results also show that writing time becomes comparable with the conventional time of 1.7 ns when the load p-n-p transistor has a saturation current of 5.0× 10¹⁷ A and a current gain of 1.0. The saturation current is 5 times larger and the current gain is 5 times smaller than those of the standard lateral p-n-p transistor