A dynamic three-state memory cell for high-density associative processors

Author

Herrmann, Frederick P. ; Keast, Craig L. ; Ishio, Keisuke ; Wade, Jon P. ; Sodini, Charles G.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA

Volume

26

Issue

4

fYear

1991

fDate

4/1/1991 12:00:00 AM

Firstpage

537

Lastpage

541

Abstract

A dynamic associative processor cell is described. The cell stores three states (0, 1, and X) and performs read, match, and masked-write functions. Five MOS transistors are used, including two overlapping dual-gate structures available in MIT´s CCD/CMOS technology. Dual-gate CCD transistors are used to reduce the charge-spooning current, which can discharge the storage node through the write transistors. The use of the cell in an associative processor is described, and experimental results are presented

Keywords

CMOS integrated circuits; charge-coupled device circuits; content-addressable storage; integrated memory circuits; parallel processing; CAM; CAS; CCD/CMOS technology; MOS transistors; dual gate CCD transistors; dynamic three-state memory cell; high-density associative processors; masked-write functions; overlapping dual-gate structures; Associative processing; CMOS technology; Central Processing Unit; Charge coupled devices; MOSFETs; Parallel processing; Random access memory; Read-write memory; Student members; System performance;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.75051

Filename

75051