Title :
A high-speed clamped bit-line current-mode sense amplifier
Author :
Blalock, Travis N. ; Jaeger, Richard C.
Author_Institution :
Dept. of Electr. Eng., Auburn Univ., AL, USA
fDate :
4/1/1991 12:00:00 AM
Abstract :
A clamped bit-line current-mode sense amplifier that maintains a low-impedance fixed potential on the bit lines is introduced. Using a general model for active-drive memory cells that include the two-transistor (2T) and three-transistor (3T) dynamic cells and the four-transistor/two-resistor (4T-2R) and six-transistor (6T) static cells, the new sense amplifier is shown to have a response speed that is insensitive to bit-line capacitance. This is achieved by relocating the large bit-line capacitance to a node within the sense amplifier that has only a minimal effect on the speed of the circuit. Bit-line clamping also minimizes inter-bit-line voltage noise coupling
Keywords :
CMOS integrated circuits; differential amplifiers; integrated memory circuits; active-drive memory cells; bit-line capacitance; clamped bit-line; current-mode; inter-bit-line voltage noise coupling; sense amplifier; CMOS memory circuits; Capacitance; Circuit noise; Circuit topology; Coupling circuits; Differential amplifiers; Latches; MOS devices; Operational amplifiers; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
