Title :
100-MHz serial access architecture for 4-Mb field memory
Author :
Miyauchi, Mayu ; Ikeda, Hiroaki ; Tsujimoto, Akira ; Sato, Yoshinori ; Tajima, Junji ; Adachi, Takao ; Hamaguchi, Kunihiro ; Fukuhara, Naohiro
Author_Institution :
NEC Corp., Kanagawa, Japan
fDate :
4/1/1991 12:00:00 AM
Abstract :
A 4-Mb field memory with a 100-MHz serial access rate has been developed. A new architecture that significantly improves serial I/O operation speed, reduces layout area, and offers simple control is proposed. To accomplish this task, a new architectural data shifter and high-speed redundancy circuit have been developed. The field memory has a 568-line×960 pixel×8-b (4,362,240 b) memory cell array designed for high-definition television (HDTV) screens. A 1.0 μm CMOS process technology is used to produce a die size of 12.94 mm×25.9 mm. The write-read cycle time is 9 ns, the access time is 8 ns, and the active current is 170 mA at a 50-MHz cycle rate with a standby current of about 3 mA
Keywords :
CMOS integrated circuits; VLSI; high definition television; integrated memory circuits; redundancy; 1 micron; 100 MHz; 170 mA; 3 mA; 4 Mbit; 50 MHz; 8 ns; 9 ns; CMOS process technology; HDTV screens; VLSI; access time; active current; architectural data shifter; field memory; high-definition television; high-speed redundancy circuit; layout area reduction; memory cell array; serial I/O operation speed; serial access architecture; standby current; video data storage; write-read cycle time; CMOS process; CMOS technology; Counting circuits; HDTV; Helium; National electric code; Read-write memory; Registers; TV; Video recording;
Journal_Title :
Solid-State Circuits, IEEE Journal of
