Title :
Design of a second-level cache chip for shared-bus multimicroprocessor systems
Author :
Uchiyama, Kunio ; Aoki, Hirokazu ; Nishii, Osamu ; Hatano, Susumu ; Nagashima, Osamu ; Oishi, Kanji ; Kitano, Jun
Author_Institution :
Hitachi Ltd., Tokyo, Japan
fDate :
4/1/1991 12:00:00 AM
Abstract :
The design of a second-level cache chip with the most suitable architecture for shared-bus multiprocessing is described. This chip supports high-speed (160-MB/s) burst transfer between multilevel caches and a newly proposed cache-consistency protocol. The chip, which supports a 50-MHz CPU and uses 0.8 μm CMOS technology, includes a 32 kB data memory, 42 kb tag memory. and 21.7 K-gate logic
Keywords :
CMOS integrated circuits; VLSI; buffer storage; integrated memory circuits; multiprocessing systems; 0.8 micron; 32 kByte; 42 kbit; 50 MHz; CMOS technology; cache-consistency protocol; high speed burst transfer; multilevel caches; multimicroprocessor systems; second-level cache chip; shared-bus; Cache memory; Circuit optimization; Control systems; Laboratories; Logic; Microprocessors; Multiprocessing systems; Protocols; System performance; System-on-a-chip;
Journal_Title :
Solid-State Circuits, IEEE Journal of
