PLL-based BiCMOS on-chip clock generator for very high-speed microprocessor

Author

Kurita, Kozaburo ; Hotta, Takashi ; Nakano, Tetsuo ; Kitamura, Nobuaki

Author_Institution

Hitachi Ltd., Ibaraki, Japan

Volume

26

Issue

4

fYear

1991

fDate

4/1/1991 12:00:00 AM

Firstpage

585

Lastpage

589

Abstract

Described is a phase-locked loop (PLL)-based BiCMOS on-chip clock generator (PCG), which is used to generate an internal clock synchronized to a reference clock from outside the chip. In order to obtain a very wide operation bandwidth, it is proposed that the PCG include a compensation circuit for voltage-controlled oscillator (VCO) operation. The compensation circuit varies the oscillation bandwidth of the VCO according to the reference clock frequency, preventing the expected oscillation frequency from being outside the oscillation bandwidth. The PCG is designed and fabricated with 1.0 μm BiCMOS technology, and it achieves an operation bandwidth of 3 to 90 MHz

Keywords

BIMOS integrated circuits; VLSI; clocks; compensation; microprocessor chips; phase-locked loops; pulse generators; synchronisation; timing circuits; variable-frequency oscillators; 1 micron; 3 to 90 MHz; 87 MHz; BiCMOS; PLL based onchip generator; VCO operation; clock generator; compensation circuit; high-speed microprocessor; internal clock; reference clock; voltage-controlled oscillator; Bandwidth; BiCMOS integrated circuits; CMOS technology; Clocks; Detectors; Frequency; Microprocessors; Phase detection; Phase locked loops; Voltage-controlled oscillators;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.75059

Filename

75059