Title :
A 10 ns 54×54 b parallel structured full array multiplier with 0.5 μm CMOS technology
Author :
Mori, Junji ; Nagamatsu, Masato ; Hirano, Masashi ; Tanaka, Shigeru ; Noda, Makoto ; Toyoshima, Yoshiaki ; Hashimoto, Kazuhiro ; Hayashida, Hiroyuki ; Maeguchi, Kenji
Author_Institution :
Toshiba Corp., Kawasaki, Japan
fDate :
4/1/1991 12:00:00 AM
Abstract :
A 54 b×54 b multiplier fabricated in a double-metal 0.5 μm CMOS technology is described. The 54 b×54 b full array is adopted to complete multiplication within one latency. A 10 ns multiplication time is achieved by optimizing both the propagation time of the part consisting of 4-2 compressors and the propagation time of the final adder part. The n-channel pass-transistor circuit and the p-channel load circuit are used at the critical blocks to improve the multiplication speed. This multiplier is intended to be applied to double-precision floating-point data processing based on the IEEE standard up to clock range of 100 MHz
Keywords :
CMOS integrated circuits; VLSI; digital arithmetic; integrated logic circuits; multiplying circuits; parallel processing; 0.5 micron; 10 ns; 100 MHz; CMOS technology; IEEE standard; clock range; compressors; double metal technology; double-precision floating-point data processing; full array multiplier; n-channel pass-transistor circuit; p-channel load circuit; parallel structured multiplier; Adders; CMOS technology; Cache memory; Circuits; Clocks; Compressors; Delay; Microprocessors; Paper technology; Pipeline processing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
