A self-learning neural network chip with 125 neurons and 10 K self-organization synapses

Author

Arima, Yutaka ; Mashiko, Koichiro ; Okada, Keisuke ; Yamada, Tsuyoshi ; Maeda, Atsushi ; Kondoh, Harufusa ; Kayano, Shimpei

Author_Institution

Mitsubishi Electr. Corp., Itami, Japan

Volume

26

Issue

4

fYear

1991

fDate

4/1/1991 12:00:00 AM

Firstpage

607

Lastpage

611

Abstract

A learning neural network LSI chip is described. The chip integrates 125 neuron units and 10K synapse units with the 1.0 μm double-poly-Si, double-metal CMOS technology. Most of this integration has been realized by using a mixed design architecture of digital and analog circuits. The fully feedback connection network LSI can memorize at least 15 patterns with 50 μs learning time for each pattern. Under the condition that each test vector keeps a Hamming distance of 6 from memorized pattern, a correct association rate of 98% is obtained. The relaxation time is 1 to 2 μs. This chip consumes less than 7.5 W

Keywords

CMOS integrated circuits; large scale integration; learning systems; microprocessor chips; neural nets; self-adjusting systems; 1 micron; 1.5 W; LSI chip; double-metal CMOS technology; double-poly-Si; feedback connection network; memorized pattern; mixed analogue/digital circuits; polycrystalline Si; self-learning neural network chip; self-organization synapses; Analog circuits; Biological neural networks; CMOS technology; Hardware; Large scale integration; Network-on-a-chip; Neural networks; Neurons; System-on-a-chip; Very large scale integration;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.75062

Filename

75062