A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3-μm CMOS

Author

Lin, Yuh-Min ; Kim, Beomsup ; Gray, Paul R.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

Volume

26

Issue

4

fYear

1991

fDate

4/1/1991 12:00:00 AM

Firstpage

628

Lastpage

636

Abstract

Described is a self-calibrated pipelined A/D converter technique potentially appropriate for such high-resolution video applications. This approach requires much less area than multistep flash approaches and requires fewer clock cycles than error averaging techniques. Since self-calibration can be performed during interframe intervals, this approach is particularly attractive for video applications. A 3-μm CMOS prototype fabricated using this architecture achieves 13-b resolution at 2.5 Msample/s. consumes 100 mW, and occupies 40 kmil² (26 mm²), with a single 5-V supply and two-phase nonoverlapping clock

Keywords

CMOS integrated circuits; analogue-digital conversion; calibration; pipeline processing; 100 mW; 2.5 MHz; 3 micron; 5 V; ADC; CMOS; high-resolution video applications; interframe intervals; monolithic IC; pipelined A/D converter; self-calibration; single 5-V supply; two-phase nonoverlapping clock; Application software; CMOS technology; Clocks; Costs; High-resolution imaging; Image resolution; Jitter; Prototypes; Sampling methods; Signal resolution;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.75065

Filename

75065