A 10-b 70-MS/s CMOS D/A converter

Author

Nakamura, Yasuyuki ; Miki, Takahiro ; Maeda, Atsushi ; Kondoh, Harufusa ; Yazawa, Nobuharu

Author_Institution

Mitsubishi Electr. Corp., Hyogo, Japan

Volume

26

Issue

4

fYear

1991

fDate

4/1/1991 12:00:00 AM

Firstpage

637

Lastpage

642

Abstract

A 10-b 70-MS/s CMOS D/A converter fabricated in a 1-μm CMOS technology is described. An integral linearity error caused by error distributions of current sources is reduced by a new switching sequence called hierarchical symmetrical switching. A differential linearity error caused by an off-axis drain-source implantation is reduced by the layout technique of current sources. The D/A converter is fabricated by using a single-polycide double-metal standard digital process. Both the integral and the differential linearity errors are less than ±0.5 LSB. The settling time to ±0.1 % is less than 14 ns. The worst-case glitch energy is approximately 60 pV-s. This D/A converter has a single power supply of 5 V and dissipates 170 mW at 70 MS/s. The chip size is 2.02 mm×1.87 mm

Keywords

CMOS integrated circuits; coding errors; digital-analogue conversion; 14 ns; 170 mW; 5 V; CMOS technology; D/A converter; DAC; current sources; differential linearity error; double-metal standard digital process; error distributions; hierarchical symmetrical switching; integral linearity error; layout technique; monolithic type; off-axis drain-source implantation; single power supply; single-polycide; switching sequence; CMOS technology; Laboratories; Large scale integration; Linearity; Matrix converters; Paper technology; Power supplies; Research and development; Symmetric matrices; Wideband;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.75066

Filename

75066