Analysis and optimization of BiCMOS digital circuit structures

Author

Embabi, S.H.K. ; Bellaouar, A. ; Elmasry, M.I.

Author_Institution

Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada

Volume

26

Issue

4

fYear

1991

fDate

4/1/1991 12:00:00 AM

Firstpage

676

Lastpage

679

Abstract

Circuit analyses and performance optimization are presented of three basic BiCMOS digital circuit structures: BiCMOS buffer, NMOS/CML (coupled-mode logic), and ECL (emitter-coupled logic)/CMOS interface circuits. The analytical modeling of the transient behavior offers insight into the critical circuit and device parameters that affect the performance of these circuits. Techniques to improve the speed of each structure and the tradeoff factors involved in designing such circuits are discussed. The derived delay expressions can also be used in CAD tools for optimizing BiCMOS circuits and systems

Keywords

BIMOS integrated circuits; buffer circuits; digital integrated circuits; integrated logic circuits; logic design; BiCMOS digital circuit structures; CAD; ECL-CMOS circuits; NMOS-CML circuits; analytical modeling; buffer; coupled-mode logic; emitter-coupled logic; performance optimization; transient behavior; BiCMOS integrated circuits; CMOS digital integrated circuits; CMOS logic circuits; Circuit analysis; Coupling circuits; Digital circuits; Logic devices; MOS devices; Optimization; Performance analysis;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.75074

Filename

75074