A 130-nm CMOS 100-Hz–6-GHz Reconfigurable Vector Signal Analyzer and Software-Defined Receiver

Author

Goel, Ankush ; Analui, Behnam ; Hashemi, Hossein

Author_Institution

MediaTek USA, San Jose, CA, USA

Volume

60

Issue

5

fYear

2012

fDate

5/1/2012 12:00:00 AM

Firstpage

1375

Lastpage

1389

Abstract

A monolithic 100-Hz-6-GHz reconfigurable vector signal analyzer (VSA) and software-defined receiver (SDR), following a two-step up-down conversion heterodyne scheme with robustness to various wideband interference scenarios and local oscillator (LO) harmonic mixing, is presented. The 130-nm CMOS chip does not require external filters or baseband processing to reduce the effect of interferences or LO harmonics. The receiver has tunable gain from -67 to 68 dB in steps of 0.5 dB, and tunable bandwidth from 0.4 to 11 MHz in steps of 0.5 MHz. The receiver sensitivity at the maximum gain is - 82 dBm. A monolithic VSA/SDR enables various commercial and military wireless solutions.

Keywords

CMOS analogue integrated circuits; interference (signal); radio receivers; software radio; spectral analysers; CMOS; LO harmonics; SDR; VSA; bandwidth 0.4 MHz to 11 MHz; frequency 100 Hz to 6 GHz; gain -67 dB to 68 dB; local oscillator harmonic mixing; monolithic reconfigurable vector signal analyzer; receiver sensitivity; size 130 nm; software-defined receiver; up-down conversion heterodyne scheme; wideband interference; Gain; Linearity; Mixers; Radio frequency; Receivers; Switches; Wideband; CMOS; RF; receiver; wideband;

fLanguage

English

Journal_Title

Microwave Theory and Techniques, IEEE Transactions on

Publisher

ieee

ISSN

0018-9480

Type

jour

DOI

10.1109/TMTT.2012.2190091

Filename

6177699