Multi-pillar surrounding gate transistor (M-SGT) for compact and high-speed circuits

Author

Nitayama, Akihiro ; Takato, Hiroshi ; Okabe, Naoko ; Sunouchi, Kazumasa ; Hieda, Katsuhiko ; Horiguchi, Fumio ; Masuoka, Fujio

Author_Institution

Toshiba Corp., Kawasaki, Japan

Volume

38

Issue

3

fYear

1991

fDate

3/1/1991 12:00:00 AM

Firstpage

579

Lastpage

583

Abstract

The M-SGT has a three-dimensional structure, which consists of the source, gate, and drain arranged vertically. The gate electrode surrounds the crowded multipillar silicon islands. Because all the sidewalls of the pillars are used effectively as the transistor channel, the M-SGT has a high-shrinkage feature. The area occupied by the M-SGT can be shrunk to less than 30% of that occupied by the planar transistor. The small occupied area and the mesh-structured gate electrode lead to the small junction capacitance and the small gate electrode RC delay, resulting in high-speed operation. The fabrication of the M-SGT CMOS inverter chain is discussed. The propagation delay reduces to 40%, compared with the planar transistor inverter chain

Keywords

CMOS integrated circuits; VLSI; capacitance; integrated circuit technology; integrated logic circuits; 3D structure; M-SGT CMOS inverter chain; Si pillar islands; ULSI; area occupied; area reduction; fabrication; high-shrinkage feature; high-speed circuits; high-speed operation; mesh-structured gate electrode; multi-pillar surrounding gate transistor; propagation delay; small gate electrode RC delay; small junction capacitance; three-dimensional structure; Capacitance; Circuits; Electrodes; Fabrication; Hot carriers; Inverters; Silicon; Space technology; Transistors; Ultra large scale integration;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.75169

Filename

75169