A 2.5-V, 12-b, 5-MSample/s pipelined CMOS ADC

Author

Yu, Paul C. ; Lee, Hae-Seung

Volume

31

Issue

12

fYear

1996

fDate

12/1/1996 12:00:00 AM

Firstpage

1854

Lastpage

1861

Abstract

A set of power minimization techniques is proposed for pipelined ADC´s. These techniques include commutating feedback-capacitors, sharing of the op-amp between the adjacent stages of the pipeline, reusing the first stage of the op-amp as comparator pre-amp, and exploiting parasitic capacitors for common-mode feedback. This set of low-power design techniques is incorporated in an experimental chip fabricated in a 1.2-μm, double-poly, double-metal CMOS process. At 12-b 5-Msample/s, the chip dissipates 33 mW of power from a 2.5-V analog supply while achieving a maximum differential nonlinearity (DNL) of -0.78 and +0.63 least-significant bits (LSB) with a peak signal-to-noise ratio (SNR) of 67.6 dB

Keywords

CMOS integrated circuits; analogue-digital conversion; circuit feedback; integrated circuit design; pipeline processing; 1.2 micron; 12 bit; 2.5 V; 33 mW; 67.6 dB; SNR; common-mode feedback; comparator pre-amp; double-poly double-metal CMOS process; feedback-capacitor commutation; low-power design techniques; op-amp sharing; parasitic capacitors; pipelined CMOS ADC; power minimization techniques; signal-to-noise ratio; CMOS process; Capacitors; Computer architecture; Feedback; Instruments; Operational amplifiers; Pipelines; Prototypes; Signal processing; Signal resolution;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.545805

Filename

545805