• DocumentCode
    1483850
  • Title

    Limits of nano-gate fabrication

  • Author

    Allee, David R. ; Broers, Alec N. ; Pease, R.W.

  • Author_Institution
    Dept. of Eng., Cambridge Univ., UK
  • Volume
    79
  • Issue
    8
  • fYear
    1991
  • fDate
    8/1/1991 12:00:00 AM
  • Firstpage
    1093
  • Lastpage
    1105
  • Abstract
    The authors review the limits of nanometer-scale gate electrode (nano-gate) fabrication. The technology to fabricate nano-gates has become increasingly important in recent years as the scaling limits of conventional electronic devices and the quantum effects of novel devices are investigated. Consistent with the technology used to fabricate virtually all of the smallest devices to date, the emphasis is on the resolution limits of electron beam lithography and associated ultrahigh resolution resists. Recent results of directly patterning SiO2 with nanometer-scale resolution by e-beam exposure through a sacrificial layer are also presented. Because the high resistance normally associated with nanometer-scale electrodes seriously limits the performance of high-frequency devices, various techniques to reduce the gate resistance are compared
  • Keywords
    electron beam lithography; electron resists; integrated circuit technology; reviews; SiO2; direct patterning; electron beam lithography; gate-resistance-reduction; high-frequency devices; monolithic IC; nano-gate fabrication; nanometer-scale gate electrode; resolution limits; review; sacrificial layer; scaling limits; ultrahigh resolution resists; Brightness; Current density; Electrodes; Electron beams; FETs; Fabrication; Frequency; Lithography; Nanoscale devices; Resists;
  • fLanguage
    English
  • Journal_Title
    Proceedings of the IEEE
  • Publisher
    ieee
  • ISSN
    0018-9219
  • Type

    jour

  • DOI
    10.1109/5.92069
  • Filename
    92069