A stereo multibit ΣΔ DAC with asynchronous master-clock interface

Author

Kwan, Tom ; Adams, Robert ; Libert, Robert

Author_Institution

Analog Devices, Santa Clara, CA, USA

Volume

31

Issue

12

fYear

1996

fDate

12/1/1996 12:00:00 AM

Firstpage

1881

Lastpage

1887

Abstract

A two-channel multibit ΣΔ audio digital-to-analog converter (DAC) with on-chip digital phase-locked loop and sample-rate converter is described. The circuit requires no over-sampled synchronous clocks to operate and rejects input sample clock jitter above 16 Hz at 6 dB/octave. A second-order modulator with a multibit quantizer, switched-capacitor (SC) DAC, and single-ended second-order SC filter provides a measured out-of-band noise of -63 dBr with less than 0.1° phase nonlinearity. Measured S/(THD+N) of the DAC channel including a 0-63 dB, 1 dB/step attenuator is greater than 90 dB unweighted. The circuit is implemented in 0.6-μm DPDM CMOS, dissipating 220 mW at 5 V. Die size is 3 mm×4 mm

Keywords

CMOS integrated circuits; Hi-Fi equipment; digital phase locked loops; digital-analogue conversion; interpolation; jitter; sigma-delta modulation; switched capacitor networks; timing; 0.6 micron; 220 mW; 5 V; DPDM CMOS; SC DAC; asynchronous master-clock interface; audio digital-to-analog converter; digital phase-locked loop; input sample clock jitter rejection; multibit quantizer; onchip digital PLL; sample-rate converter; second-order modulator; sigma-delta DAC; single-ended second-order SC filter; stereo multibit ΣΔ DAC; switched-capacitor DAC; two-channel DAC; Circuit noise; Clocks; Digital-analog conversion; Filters; Jitter; Noise measurement; Phase locked loops; Phase measurement; Phase modulation; Phase noise;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.545808

Filename

545808