Title :
An 81-MHz IF receiver in CMOS
Author :
Hairapetian, Armond
Author_Institution :
Newport Microsyst. Inc., Irvine, CA, USA
fDate :
12/1/1996 12:00:00 AM
Abstract :
An 81-MHz CMOS IF receiver for digital wireless applications is presented. The receiver consists of a continuous-time IF amplifier, a subsampling switched-capacitor gain stage, and a sixth-order bandpass ΣΔ A/D converter. Incorporating 24 dB of programmable gain, the receiver achieves 92 dB of dynamic range in a 200 kHz bandwidth. Due to its IF sampling nature, the reciever is immune to de offset, flicker noise, and errors due to mismatches between I and Q signal paths. By utilizing a pseudo two-path resonator architecture in the bandpass ΣΔ A/D converter, a stable passband center frequency which is immune to capacitor mismatch is achieved. Implemented in 0.8-μm CMOS, this chip uses a single 3 V supply and consumes 14.4 mW of power
Keywords :
CMOS integrated circuits; digital radio; radio receivers; sigma-delta modulation; switched capacitor networks; 0.8 micron; 14.4 mW; 200 kHz; 24 dB; 3 V; 81 MHz; CMOS chip; IF receiver; IF sampling; continuous-time IF amplifier; digital wireless applications; programmable gain; pseudo two-path resonator architecture; sigma-delta A/D converter; sixth-order bandpass ΣΔ ADC; stable passband center frequency; subsampling SC gain stage; switched-capacitor gain stage; 1f noise; Analog-digital conversion; Baseband; CMOS technology; Dynamic range; Frequency conversion; Narrowband; Radio frequency; Sampling methods; Signal sampling;
Journal_Title :
Solid-State Circuits, IEEE Journal of
