A multiple sampling, single A/D conversion technique for I/Q demodulation in CMOS

We have developed a CMOS A/D converter for I/Q demodulation with an analog mirror signal suppression filter in the sampling unit. The circuit directly converts a modulated 30 MHz IF signal to digitized I and Q values in the base band with an accuracy of more than 10 b. The output data rate is 2 MHz and the power consumption is 270 mW. By placing the I/Q split mirror suppression filter on the analog side, we can get a highly integrated system solution for a coherent receiver. The circuit uses multiple sampling, that gives the input values to the filter. The sizes of the sampling capacitors determine the coefficients for the filter multiplications. The sampled charges are then added in order to get the filter additions. This total charge is then converted to digital form in a single conversion. By requiring the filter to block DC, the filter subtraction becomes a part of the active offset reduction using correlated double sampling. Careful layout and very simple circuit solutions make the design possible