Title :
A 660 MB/s interface megacell portable circuit in 0.3 μm-0.7 μm CMOS ASIC
Author :
Donnelly, Kevin S. ; Chan, Yiu-Fai ; Ho, John T C ; Tran, Chanh V. ; Patel, Samir ; Lau, Benedict ; Kim, Jun ; Chau, Pak Shing ; Huang, Charlie ; Wei, Jason ; Yu, Leung ; Tarver, Richard ; Kulkami, R. ; Stark, Don ; Johnson, Mark G.
Author_Institution :
Rambus Inc., Mountain View, CA, USA
fDate :
12/1/1996 12:00:00 AM
Abstract :
A byte-wide I/O cell with 660 MB/s data rate uses low-jitter DLL-generated clocks, self-calibrated controlled-current drivers, and linear amplifier input receivers. The CAD techniques developed allow the design to be ported to CMOS processes ranging from 0.7 μm to 0.3 μm. The chip is 0.9×3.4 mm2 using 0.3 μm rules
Keywords :
CMOS integrated circuits; circuit CAD; computer interfaces; delay circuits; integrated circuit design; jitter; mixed analogue-digital integrated circuits; peripheral interfaces; timing; 0.3 to 0.7 micron; 660 MB/s; CAD techniques; CMOS ASIC; byte-wide I/O cell; delay locked loop; interface megacell portable circuit; linear amplifier input receivers; low-jitter DLL-generated clocks; self-calibrated controlled-current drivers; Application specific integrated circuits; Circuit noise; Clocks; Delay; Design automation; Driver circuits; Noise generators; Random access memory; Timing; Working environment noise;
Journal_Title :
Solid-State Circuits, IEEE Journal of
