Single-chip 4×500-MBd CMOS transceiver

Author

Widmer, Albert X. ; Wrenner, Kevin ; Ainspan, Herschel A. ; Parker, Ben ; Austruy, Pierre ; Brezzo, Bernard ; Haen, Anne-Marie ; Ewen, John F. ; Soyuer, Mehmet ; Blanc, Alain ; Abbiate, Jean-Claude ; Deutsch, Alina ; Shin, Hyun J.

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

Volume

31

Issue

12

fYear

1996

fDate

12/1/1996 12:00:00 AM

Firstpage

2004

Lastpage

2014

Abstract

A CMOS chip containing four 500-MBd serializer/deserializer pairs has been designed to relieve interconnect congestion in an ATM switch system. The 9.7×9.7 mm² chip fabricated in a 0.8-μm technology is packaged on a ceramic ball grid array and dissipates 3.5 W. It replaces a 72-wire parallel interface with an eight-line serial interface transparent to the user and supports transmission at 1.6 Gb/s per direction in full-duplex mode. Virtually error-free operation in a system environment over electrical serial links having up to 9 dB loss at 500 MHz has been realized using signal predistortion for the serial bit stream and PLL clock recovery for each of the four receivers. Interface timing and serial-link driver strength are programmable

Keywords

CMOS digital integrated circuits; asynchronous transfer mode; data communication; data communication equipment; digital communication; electronic switching systems; timing; transceivers; 0.8 micron; 1.6 Gbit/s; 3.5 W; 500 MHz; 9 dB; ATM switch system; CMOS transceiver; PLL clock recovery; ceramic BGA; ceramic ball grid array; error-free operation; full-duplex mode; interface timing; serial-link driver strength; serializer/deserializer pairs; signal predistortion; Asynchronous transfer mode; CMOS technology; Ceramics; Clocks; Electronics packaging; Error-free operation; Phase locked loops; Predistortion; Switches; Transceivers;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.545824

Filename

545824