2.8-Gb/s 176-mW byte-interleaved and 3.0-Gb/s 118-mW bit-interleaved 8:1 multiplexers with a 0.15-μm CMOS technology

Author

Kurisu, Masakazu ; Kaneko, Makoto ; Suzaki, Tetsuyuki ; Tanabe, Akira ; Togo, Mitsuhiro ; Furukawa, Akio ; Tamura, Takao ; Nakajima, Ken ; Yoshida, Kazuyoshi

Author_Institution

NEC Corp., Kawasaki, Japan

Volume

31

Issue

12

fYear

1996

fDate

12/1/1996 12:00:00 AM

Firstpage

2024

Lastpage

2029

Abstract

This paper reports the first CMOS implementation of an 8:1 byte-interleaved multiplexer (byte-MUX) operating in the Gb/s region, together with an 8:1 bit-interleaved multiplexer (bit-MUX). A future generation 0.15-μm CMOS technology has been applied. Both chips use identical bit-MUX cores with a static shift-register architecture, and have ECL interfaces with a single supply of -2 V. The byte-MUX demonstrates 43-mW/GHz dependence on clock frequency and operates up to 2.8 Gb/s with a power dissipation of 176 mW. The bit-MUX showed 20-mW/GHz dependence on clock frequency and operated up to 3.0 Gb/s with a power dissipation of 118 mW. This revel of performance has been achieved by a novel row-column exchanger configuration, critical path reduction and precise clocking techniques utilized in the bit-MUX core, and the development of high-speed I/O buffers

Keywords

CMOS digital integrated circuits; multiplexing equipment; time division multiplexing; timing; -2 V; 0.15 micron; 118 mW; 176 mW; 2.8 Gbit/s; 3 Gbit/s; CMOS technology; ECL interfaces; TDM; bit-interleaved multiplexers; byte-interleaved multiplexers; clocking techniques; critical path reduction; high-speed I/O buffers; row-column exchanger configuration; static shift-register architecture; CMOS technology; Circuits; Clocks; Frequency; Gallium arsenide; Multiplexing; Optical fiber communication; Power dissipation; SONET; Silicon;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.545826

Filename

545826