Title :
Comments on “A robust single phase clocking for low power, high-speed VLSI applications” [and reply]
Author_Institution :
Dept. of Electr. Eng., Edinburgh Univ., UK
fDate :
12/1/1996 12:00:00 AM
Abstract :
For the original article see ibid., vol. 31, no. 2, p. 247-54 (1996). The commenter points out that some of the material in a recent paper by Afghahi has been previously published. He also states that a divide-by-two circuit described therein is clock edge-sensitive rather than frequency dependent, and cannot be understood in terms of connecting two digital latches. In reply the author clarifies some aspects of his paper
Keywords :
VLSI; digital integrated circuits; flip-flops; integrated logic circuits; timing circuits; clock edge-sensitive; divide-by-two circuit; high-speed VLSI applications; latches; low power VLSI applications; ratio circuits; robust single phase clocking; Circuit simulation; Clocks; Coupling circuits; Flip-flops; Frequency dependence; Inverters; Latches; Robustness; Threshold voltage; Very large scale integration;
Journal_Title :
Solid-State Circuits, IEEE Journal of
