A high-performance half-micrometer generation CMOS technology for fast SRAMs

An advanced, high-performance, half-micrometer generation technology has been developed for fast CMOS SRAM circuits. This process features an aggressive interwell isolation module which allows scaling of the n⁺ to p⁺ space to less than 2 μm and an advanced framed-mask poly-buffered LOCOS isolation (FMPBL) which reduces field oxide encroachment and the transistor narrow-width effect and provides a 1.2-μm active pitch. Transistors are fabricated with a 125-A gate oxide and a dual n⁺/p⁺ source/drain implanted polysilicon gates to provide excellent short-channel behavior down to 0.3-μm effective channel length. Transistor design is optimized to reduce the polysilicon gate bird´s beak and lightly doped drain (LDD) underdiffusion. For PMOS transistors, boron diffusion through the gate oxide is minimized by replacing BF₂ with B ¹¹ for the p⁺ S/D implant. A titanium salicide process provides strapping between n⁺/p⁺ polysilicon gates and lower sheet and contact resistances. The back-end features three levels of metallization and polysilicon contact plugs. Discrete transistor lifetimes for DC hot-carrier degradation are in excess of 10 years at 3.3-V operation. A 16 K× 4 SRAM displayed no parametric shifts after hot-carrier stressing for 1000 h at 7-V and 0°C. This is consistent with a lifetime of greater than 10 years at 3.3-V operation. Ring oscillator delay times of 85 ps at 3.3-V and 65 ps at 5-V supply are achieved