Title :
Nonideal battery and main memory effects on CPU speed-setting for low power
Author :
Martin, Thomas L. ; Siewiorek, Daniel P.
Author_Institution :
Dept. of Electr. & Comput. Eng., Alabama Univ., Huntsville, AL, USA
Abstract :
This paper explores the system-level power-performance tradeoffs of dynamically varying CPU speed. Previous work in CPU speed-setting considered only the power of the CPU and only CPUs that vary supply voltage with frequency. This work takes a broader approach, considering total system power, battery capacity, and main memory bandwidth. The results, which are up to a factor of four less than ideal, show that all three must be considered when setting the CPU speed.
Keywords :
low-power electronics; microprocessor chips; CPU speed-setting; battery capacity; low-power design; main memory bandwidth; system-level design; total system power; Bandwidth; Batteries; Central Processing Unit; Circuits; Energy consumption; Frequency; Power dissipation; Power system modeling; Very large scale integration; Voltage;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
