Chaotic behavior and synchronization phenomena in a novel chaotic transistors circuit

Author

Pham, Cong-Kha ; Korehisa, Makoto ; Tanaka, Mamoru

Author_Institution

Dept. of Inf. Sci., Tokyo Univ. of Inf. Sci., Chiba, Japan

Volume

43

Issue

12

fYear

1996

fDate

12/1/1996 12:00:00 AM

Firstpage

1006

Lastpage

1011

Abstract

The chaotic behavior and synchronization phenomena which occur in a novel chaotic transistors circuit with high speed operation are described. The most important point is to change a nonlinear transfer characteristic of a MOS inverter to a nonlinearity generating chaos. The proposed circuit includes a looped MOS inverter having a pull-up resistor serially connected to a pull-down NMOS transistor. A switched-capacitor (SC) circuit having a hold capacitor and two CMOS switches is added in the loop of the circuit to operate sampling holding. The chaotic behavior has been found along with a variation of a sampling clock frequency. The synchronization phenomena is also found between two coupled chaotic transistors circuits. The test chip is implemented employing 2 μm CMOS technology of the MOSIS service

Keywords

CMOS integrated circuits; chaos; nonlinear network analysis; switched capacitor networks; synchronisation; CMOS technology; SC circuit; chaotic behavior; chaotic transistors circuit; high speed operation; looped MOS inverter; nonlinear transfer characteristic; pull-down NMOS transistor; pull-up resistor; sampling clock frequency; switched-capacitor circuit; synchronization phenomena; CMOS technology; Chaos; Character generation; Frequency synchronization; Inverters; MOSFETs; Resistors; Sampling methods; Switched capacitor circuits; Switching circuits;

fLanguage

English

Journal_Title

Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on

Publisher

ieee

ISSN

1057-7122

Type

jour

DOI

10.1109/81.545843

Filename

545843