Multiplexed c.c.d.s for bandwidth compression applications

A 321 -cell c.c.d. bandwidth compressor capable of analogue sampling at 100 MHz is described. This system is designed to accept data with a bandwidth of 50 MHz and subsequently to clock the data out at rates up to 2 MHz for recording on magnetic tape via a cheap, low speed a-d converter. Since power requirements are at a premium, low overall power consumption and high speed performance were essential design goals. Details of the chip architecture are given and associated driver circuitry and preliminary experimental results described.