DocumentCode
1485184
Title
Efficient fault location for globally controlled and comparison-based multistage interconnection networks
Author
Bernard, Ernst G.
Author_Institution
Inst. for Network Theory & Circuit Design, Tech. Univ. Munchen, Germany
Volume
45
Issue
12
fYear
1996
fDate
12/1/1996 12:00:00 AM
Firstpage
1420
Lastpage
1425
Abstract
Procedures for fault location in globally controlled and comparison-based multistage interconnection networks (MINs) are presented. The number of tests is constant or depends logarithmically on the network size. The tests are independent of the actual fault location and type which yields reduced time consumption and simple implementation. Furthermore, these procedures are well suited to be implemented for a built-in self test
Keywords
built-in self test; fault location; logic testing; multistage interconnection networks; bitonic merging networks; built-in self test; comparison-based; fault location; globally controlled; multistage interconnection networks; Automatic testing; Circuit faults; Circuit testing; Fault location; Fault tolerance; Integrated circuit testing; Integrated circuit yield; Multiprocessor interconnection networks; Packet switching; System testing;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/12.545971
Filename
545971
Link To Document