DocumentCode :
1485395
Title :
Through-Silicon-Via Capacitance Reduction Technique to Benefit 3-D IC Performance
Author :
Katti, Guruprasad ; Stucchi, Michele ; Van Olmen, Jan ; De Meyer, Kristin ; Dehaene, Wim
Author_Institution :
IMEC, Leuven, Belgium
Volume :
31
Issue :
6
fYear :
2010
fDate :
6/1/2010 12:00:00 AM
Firstpage :
549
Lastpage :
551
Abstract :
Through-silicon via (TSV) constitutes a key component interconnecting adjacent dies vertically to form 3-D integrated circuits. In this letter, we propose a method to exploit the TSV C-V behavior in a p-silicon substrate to achieve minimum TSV capacitance during 3-D circuit operation. The nature of the TSV C-V characteristics depends both on TSV architecture and TSV manufacturing process, and both these factors should be optimized to obtain the minimum depletion capacitance in the desired operating voltage region. Measured C-V characteristics of the TSV demonstrate the effectiveness of the method.
Keywords :
capacitance; silicon; three-dimensional integrated circuits; 3D IC performance; C-V behavior; minimum depletion capacitance; through-silicon-via capacitance reduction; 3-D integrated circuits; TSV capacitance; Through-silicon via (TSV);
fLanguage :
English
Journal_Title :
Electron Device Letters, IEEE
Publisher :
ieee
ISSN :
0741-3106
Type :
jour
DOI :
10.1109/LED.2010.2046712
Filename :
5460909
Link To Document :
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