DocumentCode :
1485462
Title :
Analysis and On-Chip Monitoring of Gate Oxide Breakdown in SRAM Cells
Author :
Ahmed, Fahad ; Milor, Linda
Author_Institution :
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
Volume :
20
Issue :
5
fYear :
2012
fDate :
5/1/2012 12:00:00 AM
Firstpage :
855
Lastpage :
864
Abstract :
Scaling of device sizes has reduced gate oxide thickness to a few atomic layers, increasing the vulnerability of the gate oxide to breakdown. During breakdown, devices go through a gradual wearout process characterized by increased leakage. Using experimentally verified gate oxide breakdown models, a detailed analysis of the effect of progressive gate oxide breakdown on the performance of a conventional 6T SRAM cell is presented for 45-nm predictive technology. The DC margins (read, write, and retention) and access times (read and write) during wearout are analyzed, and a cell breakdown point due to degradation in each of these parameters is defined. A combination of these results is used to formulate a definition for the hard-breakdown point of a cell. An on-chip process, voltage, and temperature tolerant monitoring scheme is proposed to detect the gradual wearout of SRAM cells. The monitoring scheme enables the detection of impending cell failure, which in turn can trigger reconfiguration of the SRAM with redundant rows and/or columns prior to failure.
Keywords :
SRAM chips; monitoring; SRAM cells; cell breakdown point; gate oxide breakdown model; gradual wearout process; hard-breakdown point; on-chip monitoring; on-chip process; predictive technology; temperature tolerant monitoring; Degradation; Electric breakdown; Latches; Logic gates; MOS devices; Monitoring; Random access memory; Gate oxide breakdown (GOBD); on-chip monitor; reliability; testing;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2011.2119500
Filename :
5740979
Link To Document :
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